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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
·
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
·
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
·
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT573
Octal D-type transparent latch;
3-state
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74HC/HCT573
FEATURES
GENERAL DESCRIPTION
the D
n
inputs enter the latches. In this
condition the latches are transparent,
i.e. a latch output will change state
each time its corresponding D-input
changes.
When LE is LOW the latches store the
information that was present at the
D-inputs a set-up time preceding the
HIGH-
to-L
OW transition of LE.
When OE is LOW, the contents of the
8 latch
es
are available at the outputs.
When OE is HIGH, the outputs go to
the high impeda
nce
OFF-state.
Operation of the OE input does not
affect the state of the latches.
·
Inputs and outputs on opposite
sides of package allowing easy
interface with microprocessors
The 74HC/HCT573 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard no.
7A.
The 74HC/HCT573 are octal D-type
transparent latches featuring
separate D-type inputs for each latch
and 3-state outputs for bus oriented
applications.
A latch enable
(LE
) input and an
output enable (OE) input are common
to all latches.
·
Useful as input or output port for
microprocessors/microcomputers
·
3-state non-inverting outputs for
bus oriented applications
·
Common 3-state output enable
input
·
Functionally identical to the “563”
and “373”
·
Output capability: bus driver
·
I
CC
category: MSI
The “573” is functionally identical to
the “563” and “373”, but the “563” has
inverted outputs and the “373” has a
different pin arrangement.
The “573” consists of eight D-type
transparent latches with 3-state true
outputs. When LE is HIGH, data at
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25
°
C; t
r
=t
f
= 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
HCT
t
PHL/
t
PLH
propagation delay
C
L
= 15 pF; V
CC
=5 V
D
n
to Q
n
14
17
ns
LE to Q
n
15
15
ns
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per latch notes 1 and 2
26
26
pF
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
m
W):
f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz
å
P
D
=C
PD
´
V
CC
2
´
f
i
+
å
(C
L
´
V
CC
2
´
f
o
) = sum of outputs
C
L
= output load capacitance in pF; V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
; for HCT the condition is V
I
= GND to V
CC
-
1.5 V
(C
L
´
V
CC
2
´
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
December 1990
2
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74HC/HCT573
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
2, 3, 4, 5, 6, 7, 8, 9
D
0
to D
7
data inputs
11
LE
latch enable input (active HIGH)
1
OE
3-state output enable input (active LOW)
10
GND
ground (0 V)
19, 18, 17, 16, 15, 14, 13, 12
Q
0
to Q
7
3-state latch outputs
20
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74HC/HCT573
FUNCTION TABLE
OPERATING
MODES
INPUTS
INTERNAL
LATCHES
OUTPUTS
OE LE D
N
Q
0
to Q
7
enable and read
register
(transparent mode)
L
L
H
H
L
H
L
H
L
H
latch and read
register
L
L
L
L
l
h
L
H
L
H
latch register and
disable outputs
H
H
L
L
l
h
L
H
Z
Z
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW
LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW
LE transition
Z = high impedance OFF-state
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74HC/HCT573
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
=t
f
= 6 ns; C
L
= 50 pF
T
amb
(
°
C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
+25
-
40 to +85
-
40 to +125
V
CC
(V)
WAVEFORMS
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
D
n
to Q
n
47
17
14
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propagation delay
LE to Q
n
50
18
14
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.7
t
PZH
/ t
PZL
3-stat
e o
utput enable
time OE to Q
n
44
16
13
140
28
24
175
35
30
210
42
36
ns
2.0
4.5
6.0
Fig.8
t
PHZ
/ t
PLZ
3-stat
e o
utput disable
time OE to Q
n
55
20
16
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.8
t
THL
/ t
TLH
output transition time
14
5
4
60
12
10
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.6
t
W
enable pulse width
HIGH
80
16
14
14
5
4
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.7
t
su
set-up time
D
n
to LE
50
10
9
11
4
3
65
13
11
75
15
13
ns
2.0
4.5
6.0
Fig.9
t
h
hold time
D
n
to LE
5
5
5
3
1
1
5
5
5
5
5
5
ns
2.0
4.5
6.0
Fig.9
December 1990
5
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
·
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
·
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
·
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT573
Octal D-type transparent latch;
3-state
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74HC/HCT573
FEATURES
GENERAL DESCRIPTION
the D
n
inputs enter the latches. In this
condition the latches are transparent,
i.e. a latch output will change state
each time its corresponding D-input
changes.
When LE is LOW the latches store the
information that was present at the
D-inputs a set-up time preceding the
HIGH-
to-L
OW transition of LE.
When OE is LOW, the contents of the
8 latch
es
are available at the outputs.
When OE is HIGH, the outputs go to
the high impeda
nce
OFF-state.
Operation of the OE input does not
affect the state of the latches.
·
Inputs and outputs on opposite
sides of package allowing easy
interface with microprocessors
The 74HC/HCT573 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard no.
7A.
The 74HC/HCT573 are octal D-type
transparent latches featuring
separate D-type inputs for each latch
and 3-state outputs for bus oriented
applications.
A latch enable
(LE
) input and an
output enable (OE) input are common
to all latches.
·
Useful as input or output port for
microprocessors/microcomputers
·
3-state non-inverting outputs for
bus oriented applications
·
Common 3-state output enable
input
·
Functionally identical to the “563”
and “373”
·
Output capability: bus driver
·
I
CC
category: MSI
The “573” is functionally identical to
the “563” and “373”, but the “563” has
inverted outputs and the “373” has a
different pin arrangement.
The “573” consists of eight D-type
transparent latches with 3-state true
outputs. When LE is HIGH, data at
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25
°
C; t
r
=t
f
= 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
HCT
t
PHL/
t
PLH
propagation delay
C
L
= 15 pF; V
CC
=5 V
D
n
to Q
n
14
17
ns
LE to Q
n
15
15
ns
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per latch notes 1 and 2
26
26
pF
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
m
W):
f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz
å
P
D
=C
PD
´
V
CC
2
´
f
i
+
å
(C
L
´
V
CC
2
´
f
o
) = sum of outputs
C
L
= output load capacitance in pF; V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
; for HCT the condition is V
I
= GND to V
CC
-
1.5 V
(C
L
´
V
CC
2
´
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
December 1990
2
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74HC/HCT573
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
2, 3, 4, 5, 6, 7, 8, 9
D
0
to D
7
data inputs
11
LE
latch enable input (active HIGH)
1
OE
3-state output enable input (active LOW)
10
GND
ground (0 V)
19, 18, 17, 16, 15, 14, 13, 12
Q
0
to Q
7
3-state latch outputs
20
V
CC
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74HC/HCT573
FUNCTION TABLE
OPERATING
MODES
INPUTS
INTERNAL
LATCHES
OUTPUTS
OE LE D
N
Q
0
to Q
7
enable and read
register
(transparent mode)
L
L
H
H
L
H
L
H
L
H
latch and read
register
L
L
L
L
l
h
L
H
L
H
latch register and
disable outputs
H
H
L
L
l
h
L
H
Z
Z
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW
LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW
LE transition
Z = high impedance OFF-state
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990
4
Philips Semiconductors
Product specification
Octal D-type transparent latch; 3-state
74HC/HCT573
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
=t
f
= 6 ns; C
L
= 50 pF
T
amb
(
°
C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
UNIT
+25
-
40 to +85
-
40 to +125
V
CC
(V)
WAVEFORMS
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
D
n
to Q
n
47
17
14
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propagation delay
LE to Q
n
50
18
14
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.7
t
PZH
/ t
PZL
3-stat
e o
utput enable
time OE to Q
n
44
16
13
140
28
24
175
35
30
210
42
36
ns
2.0
4.5
6.0
Fig.8
t
PHZ
/ t
PLZ
3-stat
e o
utput disable
time OE to Q
n
55
20
16
150
30
26
190
38
33
225
45
38
ns
2.0
4.5
6.0
Fig.8
t
THL
/ t
TLH
output transition time
14
5
4
60
12
10
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.6
t
W
enable pulse width
HIGH
80
16
14
14
5
4
100
20
17
120
24
20
ns
2.0
4.5
6.0
Fig.7
t
su
set-up time
D
n
to LE
50
10
9
11
4
3
65
13
11
75
15
13
ns
2.0
4.5
6.0
Fig.9
t
h
hold time
D
n
to LE
5
5
5
3
1
1
5
5
5
5
5
5
ns
2.0
4.5
6.0
Fig.9
December 1990
5
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